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summertrain
[专家分：0] 发布于 2005-07-13 09:23:00
集成电路设计Verilog/FPGA出国与就业暑假指导班
上海浦东新区后生集成电路培训中心 http://www.hwswworld.com
培训演示课程详见http://www.hwswworld.com/a5train
培训对象 所有有志出国或高薪就业者 开课地点 上海浦东软件园
培训时间（周五至周一，上午九点至下午四点）：
第一期: 7/22 - 7/25 第二期: 8/5 - 8/8 第三期: 8/19 - 8/22
培训教材 培训中心自编英文讲义及影印般专业英文教材
培训费用 每人每期3000元，全日制在校生凭有效身份证及学生证享受优惠每人每期1500元。其中包括讲课，实验，现场讨论,英文教材、英文讲义、工作午餐及结业证书
联系电话 021-5080-2811，5080-2813, 5131-4066 传真 021-5131-4176
联系人 陆小姐 Email training@hwswworld.com
课程介绍 Program Agenda (Subject to Change Without Notice)
1. Opening Remark
2. RTL Design under From Algorithm to System Context
3. Verilog for HARDWARE Design – Part I
4. FPGA Design: The State-of-the-Art
5. Verilog for HARDWARE Design – Part II
6. The Essence of RTL Design
7. RTL Design Using ASM
8. Open Discussion
Lab 1 Design a N Bit ALU in Behavioral View
1. Hard-wired Controller based RTL Design with ASM for Speed & Cost
2. Advanced Verilog for RTL Design – Part I
3. Verilog Design for HARDWARE Design – Part III
4. Verilog for HARDWARE Design – Part IV
5. Real Life Digital Design Strategies and Techniques
6. Case Study: Design a Pipelining FFT (Fast Fourier Transform) Block
7. Open Discussion
Lab2 Design a N Bit Shift-Subtract-based Division Machine based on N Bit ALU
1. Issues in Real Life Digital Design
2. Programmable Controller based RTL Design with ASM for Speed & Cost
3. Building Blocks in Real Life Digital Design
4. Advanced Verilog for RTL Design – Part II
5. Case Study: Design CISC (PDP-8 subset) & RISC (ARM subset) CPU Using ASM
6. Libraries, Reusable Modules and IP
7. Open Discussion
Lab 3 Design a Datapath Consists of a N Bit Division Machine with read FIFO IP & Write FIFO IP under Hardwired FSM Control
上海浦东新区后生集成电路培训中心 http://www.hwswworld.com
培训演示课程详见http://www.hwswworld.com/a5train
培训对象 所有有志出国或高薪就业者 开课地点 上海浦东软件园
培训时间（周五至周一，上午九点至下午四点）：
第一期: 7/22 - 7/25 第二期: 8/5 - 8/8 第三期: 8/19 - 8/22
培训教材 培训中心自编英文讲义及影印般专业英文教材
培训费用 每人每期3000元，全日制在校生凭有效身份证及学生证享受优惠每人每期1500元。其中包括讲课，实验，现场讨论,英文教材、英文讲义、工作午餐及结业证书
联系电话 021-5080-2811，5080-2813, 5131-4066 传真 021-5131-4176
联系人 陆小姐 Email training@hwswworld.com
课程介绍 Program Agenda (Subject to Change Without Notice)
1. Opening Remark
2. RTL Design under From Algorithm to System Context
3. Verilog for HARDWARE Design – Part I
4. FPGA Design: The State-of-the-Art
5. Verilog for HARDWARE Design – Part II
6. The Essence of RTL Design
7. RTL Design Using ASM
8. Open Discussion
Lab 1 Design a N Bit ALU in Behavioral View
1. Hard-wired Controller based RTL Design with ASM for Speed & Cost
2. Advanced Verilog for RTL Design – Part I
3. Verilog Design for HARDWARE Design – Part III
4. Verilog for HARDWARE Design – Part IV
5. Real Life Digital Design Strategies and Techniques
6. Case Study: Design a Pipelining FFT (Fast Fourier Transform) Block
7. Open Discussion
Lab2 Design a N Bit Shift-Subtract-based Division Machine based on N Bit ALU
1. Issues in Real Life Digital Design
2. Programmable Controller based RTL Design with ASM for Speed & Cost
3. Building Blocks in Real Life Digital Design
4. Advanced Verilog for RTL Design – Part II
5. Case Study: Design CISC (PDP-8 subset) & RISC (ARM subset) CPU Using ASM
6. Libraries, Reusable Modules and IP
7. Open Discussion
Lab 3 Design a Datapath Consists of a N Bit Division Machine with read FIFO IP & Write FIFO IP under Hardwired FSM Control